10:50
A UVM SystemVerilog Testbench for Directed & Random Testing of an AMS LDO Voltage Regulator
43:51
[5/5] UCIe PHY Modeling and Simulation with XMODEL / UCIe Logical Layer Modeling & Simulation
34:17
[4/5] UCIe PHY Modeling and Simulation with XMODEL / UCIe Electrical Layer Modeling (Part 3)
18:49
[3/5] UCIe PHY Modeling and Simulation with XMODEL / UCIe Electrical Layer Modeling (Part 2)
28:42
[2/5] UCIe PHY Modeling and Simulation with XMODEL / UCIe Electrical Layer Modeling (Part 1)
24:27
[1/5] UCIe PHY Modeling and Simulation with XMODEL / UCIe Overview and Introduction to XMODEL
15:30
Low-Dropout (LDO) Regulator Modeling with XMODEL | XMODEL - Scientific Analog
10:00
A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers
01:41:12
Harnessing the Power of UVM for AMS Verification with XMODEL (Part 1)
51:18
Harnessing the Power of UVM for AMS Verification with XMODEL (Part 2)
01:37:43
Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification
01:14:51
Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: A Pipelined ADC
14:55
[09-10/10] Writing OOP-style SystemVerilog Testbench for Analog IPs
10:19
[08/10] Writing OOP-style SystemVerilog Testbench for Analog IPs
09:47
[07/10] Writing OOP-style SystemVerilog Testbench for Analog IPs
05:41
[06/10] Writing OOP-style SystemVerilog Testbench for Analog IPs
07:53
[05/10] Writing OOP-style SystemVerilog Testbench for Analog IPs
08:07
[04/10] Writing OOP-style SystemVerilog Testbench for Analog IPs
06:47
[03/10] Writing OOP-style SystemVerilog Testbench for Analog IPs
12:27
[02/10] Writing OOP-style SystemVerilog Testbench for Analog IPs
16:23
[01/10] Writing OOP-style SystemVerilog Testbench for Analog IPs
07:59
XMODEL Teaser + Introduction: The Best Way to Verify Analog Circuits in SystemVerilog
05:26
XMODEL Introduction | Scientific Analog | XMODEL, GLISTER, and MODELZEN
37:04
Scientific Analog Webinar
08:09
Top-Down Modeling of SAR-ADC with XMODEL | Scientific Analog
06:55
Modeling Silicon Photonic Systems with XMODEL | Scientific Analog
12:23
Bottom-up Modeling of Phase-Locked Loop with MODELZEN | Scientific Analog
12:09
Bottom-up Modeling of DC-DC Converter with MODELZEN | Scientific Analog
04:18
User-Defined Models (UDM) of MODELZEN | Scientific Analog
02:36
Teaser: The Best Way to Verify Analog Circuits in SystemVerilog | XMODEL | Scientific Analog
10:59
[Demo] Learning XMODEL Primitives with Phase-Locked Loop Modeling | Scientific Analog
07:29
[Demo] Quick Tour on MODELZEN | Scientific Analog
07:46
[Demo] Quick Tour on GLISTER | Scientific Analog
14:55
[Demo] Quick Tour on XMODEL | Scientific Analog
05:57
Bottom-up Model Generation with MODELFIT | XMODEL - Scientific Analog
07:30
Bottom-up Model Generation with MODELZEN | XMODEL - Scientific Analog
07:49
Co-simulating XMODEL with SPICE | XMODEL - Scientific Analog
11:24
Using XMODEL in Cadence Virtuoso | XMODEL - Scientific Analog